Memory interfaces that are used to connect a memory device with some other circuit or device, such as an integrated circuit, contain numerous inputs and outputs (such as “pads”, which are the connection points to the integrated circuit) for data lines used to write and read data to a memory device, as well as clock and strobe signals, and command and address data. In particular, a memory interface may be tuned through the use of adjustable delay lines and by adjusting pad driving strengths to optimize the performance of the memory interface. This becomes particularly important when interfacing with memory devices such as double data rate (DDR) SDRAMs or other high speed data devices where the aggregation of time and delays degrade the performance of the memory interface.
In order to optimize the performance of a memory interface, it is known to tune or find the optimal values of parameters such as the delay line timing and pad drive strength in order to optimize the memory interface. The process of tuning the memory interface may be performed manually, but this process is time consuming and requires external equipment connected to the memory interface. In order to make tuning less onerous, it is known to employ a built-in self test (BIST or an MCBIST for a memory controller, in particular) on an integrated circuit to test the memory interface without external equipment. Such BISTs, however, are typically not programmable in a significant manner and are implemented to utilize resources of the chip in which the BIST is located that are normally used for other functions of the chip. Moreover, known BISTs employ fixed data patterns to test the memory interface. Accordingly, these BISTs cannot provide deterministic worst case data patterns that more likely ensure testing of the memory interface is robust and thorough.